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Inter-Integrated Circuit
of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of
their idle states.
9.4.1.2
Slave address transmission
The first byte of data transferred immediately after the START signal is the slave address transmitted by
the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
1 = Read transfer, the slave transmits data to the master.
0 = Write transfer, the master transmits data to the slave.
Only the slave with a calling address that matches the one transmitted by the master responds by sending
back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 9-9 on
page 168 ).
No two slaves in the system may have the same address. If the I 2 C module is the master, it must not
transmit an address that is equal to its own slave address. The I 2 C cannot be master and slave at the same
time. However, if arbitration is lost during an address cycle, the I 2 C reverts to slave mode and operates
correctly even if it is being addressed by another master.
9.4.1.3
Data transfer
Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction
specified by the R/W bit sent by the calling master.
All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address
information for the slave device.
Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while
SCL is high as shown in Figure 9-9 on page 168 . There is one clock pulse on SCL for each data bit, the
MSB being transferred first. Each data byte is followed by a 9th (acknowledge) bit that is signalled from
the receiving device. An acknowledge is signalled by pulling the SDA low at the ninth clock. In summary,
one complete data transfer needs nine clock pulses.
If the slave receiver does not acknowledge the master in the 9th bit time, the SDA line must be left high
by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer.
If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave
interprets this as an end of data transfer and releases the SDA line.
In either case, the data transfer is aborted and the master does one of two things:
? Relinquishes the bus by generating a STOP signal.
? Commences a new calling by generating a repeated START signal.
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
Freescale Semiconductor, Inc.
169
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